The short-loop process tuning & yield evaluation by using the addressable failure site test structures (AFS-TS)

This work describes the implementation of a novel test structure called addressable failure site test structure (AFS-TS) for via process optimization including the liner layer and W-CVD filling process. It manifests the design, defect detection and yield analysis of addressable failure site test structures. The novel test structures are used to discriminate the yield loss issues based on the high spatial defect detection resolution within 2000/spl times/2200 /spl mu/m/sup 2/ of interconnect test structures. A test chip of 4.0/spl times/6.6 mm/sup 2/ containing nine types of test structures was implemented using 0.25 /spl mu/m logic backend of line process. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.