低功耗固定宽度阵列乘法器

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI:10.1145/1013235.1013311

Jinn-Shyan Wang, C. Kuo, Tsung-Han Yang

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引用次数: 47

摘要

提出了一种用从左到右算法进行部分积约简的定宽乘法器。该设计提供的高速特性用于换取低功耗。在一种设计中，所提出的乘法器不仅速度提高了8%，而且功率提高了14%，面积减少了13%。当应用电压缩放来平衡速度时，功率降低增加到29%。

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Low-power fixed-width array multipliers

A fixed-width multiplier using the left-to-right algorithm for partial-product reduction is presented. The high-speed feature offered by this design is used to trade for low power. In one design, the proposed multiplier not only owns 8% speed improvement but also gains 14% power and 13% area reduction. When applying the voltage scaling to balance the speed, the power reduction is increased to 29%.

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来源期刊

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

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