Investigation of Window Instability in Program/Erase Cycling of TANOS NAND Flash Memory

TANOS endurance is mainly governed by interface traps at the substrate-tunnel oxide interface, generated upon electrical stress, rather than by fixed charge in the tunnel oxide/blocking dielectric or by incomplete charge compensation in the nitride. As a result of acceptor resp. donor trap formation in the upper resp. lower half of the Si band gap, the V,h program/erase window monotonically shifts upward whereas the V fb window exhibits turn-around behavior. Interface trap generation rate is highest during the erase operation and depends also on the memory stack process.