模拟亚100纳米栅极长度器件的线边缘粗糙度效应

2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502) Pub Date : 2000-09-06 DOI:10.1109/SISPAD.2000.871225

P. Oldiges, Qinghuang Lint, Karen Petrillot, Martha Sanchez, M. Ieong, M. Hargrove

{"title":"模拟亚100纳米栅极长度器件的线边缘粗糙度效应","authors":"P. Oldiges, Qinghuang Lint, Karen Petrillot, Martha Sanchez, M. Ieong, M. Hargrove","doi":"10.1109/SISPAD.2000.871225","DOIUrl":null,"url":null,"abstract":"A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device \"slices\" sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"152","resultStr":"{\"title\":\"Modeling line edge roughness effects in sub 100 nanometer gate length devices\",\"authors\":\"P. Oldiges, Qinghuang Lint, Karen Petrillot, Martha Sanchez, M. Ieong, M. Hargrove\",\"doi\":\"10.1109/SISPAD.2000.871225\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device \\\"slices\\\" sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters.\",\"PeriodicalId\":132609,\"journal\":{\"name\":\"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)\",\"volume\":\"257 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-09-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"152\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.2000.871225\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2000.871225","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 152

摘要

提出了一种快速估计线边缘粗糙度影响的方法。这种方法是基于使用多个2D器件“片”夹在一起形成给定宽度的MOS晶体管。通过与全三维模拟的比较，验证了该方法能够准确地表示毛边MOS晶体管。随后的统计研究显示了线边缘粗糙度的变化如何影响几个关键设备参数的值和方差。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Modeling line edge roughness effects in sub 100 nanometer gate length devices

A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device "slices" sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)

自引率

0.00%

发文量