高密度记忆体产品的间隔蚀刻优化，以消除磁芯泄漏故障

2007 International Symposium on Semiconductor Manufacturing Pub Date : 2007-10-01 DOI:10.1109/ISSM.2007.4446867

E. Dharmarajan, Shengnian Song, L. Mclaughlin, J. Guan, J. Gazda, E. Lin, W. Qi, H. Shiraiwa, J. Hussey, J. Lansford, B. Banerjee

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引用次数: 0

摘要

通过这项工作，我们提出了我们的90 nm高密度存储产品的核心泄漏失效机制，发现这与蚀刻工艺对高密度的加载灵敏度有关。过程优化，以解决问题，同时保持足够的蚀刻余量对字符串。

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Spacer etch optimization on high density memory products to eliminate core leakage failures

Through this work, we present a core leakage failure mechanism in our 90 nm high density memory products which was found to be related to etch process loading sensitivity to high density. Process optimization was done to fix the problem while maintaining sufficient etch margin against stringers.

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2007 International Symposium on Semiconductor Manufacturing

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