{"title":"算法验证和硬件设计的交互方法","authors":"M. Lazarescu, M. Sartori","doi":"10.1109/SMICND.1996.557380","DOIUrl":null,"url":null,"abstract":"In this paper we will describe a modality to speed up the design of the VLSI digital (mainly DSP) circuits and to reduce the design errors by increasing the interaction between the ad-hoc software program developed to validate the algorithm and the VHDL description and simulation. A real case of a digital power analyzer will be used for exemplification.","PeriodicalId":266178,"journal":{"name":"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Algorithm validation and hardware design interactive approach\",\"authors\":\"M. Lazarescu, M. Sartori\",\"doi\":\"10.1109/SMICND.1996.557380\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we will describe a modality to speed up the design of the VLSI digital (mainly DSP) circuits and to reduce the design errors by increasing the interaction between the ad-hoc software program developed to validate the algorithm and the VHDL description and simulation. A real case of a digital power analyzer will be used for exemplification.\",\"PeriodicalId\":266178,\"journal\":{\"name\":\"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMICND.1996.557380\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.1996.557380","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Algorithm validation and hardware design interactive approach
In this paper we will describe a modality to speed up the design of the VLSI digital (mainly DSP) circuits and to reduce the design errors by increasing the interaction between the ad-hoc software program developed to validate the algorithm and the VHDL description and simulation. A real case of a digital power analyzer will be used for exemplification.
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