{"title":"先进CMOS/SOI技术中锁相环、I/O和混合信号电路的设计挑战","authors":"H. Sánchez","doi":"10.1109/DCAS.2004.1360442","DOIUrl":null,"url":null,"abstract":"This article presents the technology landscape and the directions of the industry in the design of phase locked loops, input-output and mixed signal circuits in CMOS/SOI technology. It discusses the issues considered in the design of the circuits such as market pressures, productivity and the technology characteristics.","PeriodicalId":185376,"journal":{"name":"Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design challenges of PLL, I/O, and mixed signal circuits in advanced CMOS/SOI technologies\",\"authors\":\"H. Sánchez\",\"doi\":\"10.1109/DCAS.2004.1360442\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents the technology landscape and the directions of the industry in the design of phase locked loops, input-output and mixed signal circuits in CMOS/SOI technology. It discusses the issues considered in the design of the circuits such as market pressures, productivity and the technology characteristics.\",\"PeriodicalId\":185376,\"journal\":{\"name\":\"Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCAS.2004.1360442\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2004.1360442","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design challenges of PLL, I/O, and mixed signal circuits in advanced CMOS/SOI technologies
This article presents the technology landscape and the directions of the industry in the design of phase locked loops, input-output and mixed signal circuits in CMOS/SOI technology. It discusses the issues considered in the design of the circuits such as market pressures, productivity and the technology characteristics.
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