{"title":"时序自适应消噪器的fpga实现","authors":"M. Bahoura, H. Ezzaidi","doi":"10.1109/ICM.2009.5418650","DOIUrl":null,"url":null,"abstract":"This paper presents a sequential architecture of a pipelined LMS-based adaptive noise cancellation to remove the power-line interference (50/60 Hz) from electrocardiogram (ECG). This architecture is implemented on on FPGA using XUP Virtex-II Pro development board and Xilinx System Generator (XSG). The proposed architecture was evaluated using real ECG signals from the MIT-BIH database. Hardware requirement of this adaptive noise canceller is presented for various filter lengths.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"160 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"38","resultStr":"{\"title\":\"FPGA-implementation of a sequential adaptive noise canceller using Xilinx System Generator\",\"authors\":\"M. Bahoura, H. Ezzaidi\",\"doi\":\"10.1109/ICM.2009.5418650\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a sequential architecture of a pipelined LMS-based adaptive noise cancellation to remove the power-line interference (50/60 Hz) from electrocardiogram (ECG). This architecture is implemented on on FPGA using XUP Virtex-II Pro development board and Xilinx System Generator (XSG). The proposed architecture was evaluated using real ECG signals from the MIT-BIH database. Hardware requirement of this adaptive noise canceller is presented for various filter lengths.\",\"PeriodicalId\":391668,\"journal\":{\"name\":\"2009 International Conference on Microelectronics - ICM\",\"volume\":\"160 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"38\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Conference on Microelectronics - ICM\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2009.5418650\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Microelectronics - ICM","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2009.5418650","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 38
摘要
本文提出了一种基于流水线lms的自适应降噪的顺序结构，用于去除电力线干扰(50/60 Hz)。该架构采用XUP Virtex-II Pro开发板和Xilinx System Generator (XSG)在FPGA上实现。使用来自MIT-BIH数据库的真实心电信号对所提出的架构进行了评估。给出了各种滤波器长度对自适应消噪器的硬件要求。
FPGA-implementation of a sequential adaptive noise canceller using Xilinx System Generator
This paper presents a sequential architecture of a pipelined LMS-based adaptive noise cancellation to remove the power-line interference (50/60 Hz) from electrocardiogram (ECG). This architecture is implemented on on FPGA using XUP Virtex-II Pro development board and Xilinx System Generator (XSG). The proposed architecture was evaluated using real ECG signals from the MIT-BIH database. Hardware requirement of this adaptive noise canceller is presented for various filter lengths.
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