Impact of energy contamination of ultra-low energy implants on sub-0.1-μm CMOS device performance

The critical amount of implantation energy contamination is determined at which sub-0.1-μm CMOS device performance is modified. Source/drain extensions of PMOS and NMOS transistors, with physical gate lengths down to 65nm, were implanted without energy contamination (drift mode) with BF2+ and As+ at 1 keV. Subsequently several energy contamination amounts were added intentionally: source/drain extensions were implanted at the energy corresponding to the extraction voltage used in the standard acceleration / deceleration mode with a dose corresponding to the ratio of targeted energy contamination (from 0 up to 4% of the dose implanted in drift mode). Short-channel effect, Ion/Ioff tradeoff, and sub-threshold performance are analyzed for technologies from 0.18μm down to 65nm and compared to results obtained using the standard mode of implantation. The critical amount of energy contamination for each technology node is determined and compared to implanter capabilities. The scalability of current implanters down to 70nm technology node is discussed.