{"title":"一种新的可编程逻辑阵列表示，以方便测试和逻辑设计","authors":"Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu","doi":"10.1109/TENCON.1993.320051","DOIUrl":null,"url":null,"abstract":"Presents a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). Through this graph model, most realistic PLA faults, including crosspoint, stuck-at, break and bridging faults, can be modeled. The work of diagnosis and test generation is thus simplified. Also, many logic design problems, such as folding, minimization and decomposition, can be done using this representation.<<ETX>>","PeriodicalId":110496,"journal":{"name":"Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A new representation for programmable logic arrays to facilitate testing and logic design\",\"authors\":\"Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu\",\"doi\":\"10.1109/TENCON.1993.320051\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presents a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). Through this graph model, most realistic PLA faults, including crosspoint, stuck-at, break and bridging faults, can be modeled. The work of diagnosis and test generation is thus simplified. Also, many logic design problems, such as folding, minimization and decomposition, can be done using this representation.<<ETX>>\",\"PeriodicalId\":110496,\"journal\":{\"name\":\"Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TENCON.1993.320051\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCON.1993.320051","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new representation for programmable logic arrays to facilitate testing and logic design
Presents a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). Through this graph model, most realistic PLA faults, including crosspoint, stuck-at, break and bridging faults, can be modeled. The work of diagnosis and test generation is thus simplified. Also, many logic design problems, such as folding, minimization and decomposition, can be done using this representation.<>
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