小型化VLSI电路的良率估计

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI:10.1109/DFTVS.1999.802869

W. Pleskacz

{"title":"小型化VLSI电路的良率估计","authors":"W. Pleskacz","doi":"10.1109/DFTVS.1999.802869","DOIUrl":null,"url":null,"abstract":"This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find a scaling factor of the IC design which is optimal from the manufacturing yield point of view. It also allows us to reduce time-consuming extraction of the critical area functions. Examples of yield calculations using the proposed method are presented as well.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"799 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Yield estimation of VLSI circuits with downscaled layouts\",\"authors\":\"W. Pleskacz\",\"doi\":\"10.1109/DFTVS.1999.802869\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find a scaling factor of the IC design which is optimal from the manufacturing yield point of view. It also allows us to reduce time-consuming extraction of the critical area functions. Examples of yield calculations using the proposed method are presented as well.\",\"PeriodicalId\":448322,\"journal\":{\"name\":\"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)\",\"volume\":\"799 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1999.802869\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1999.802869","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

本文介绍了亚微米VLSI电路布局缩放的成品率估计方法。该方法从制造良率的角度出发，为寻找最优的集成电路设计比例因子提供了可行性。它还允许我们减少对关键区域函数的耗时提取。并给出了用该方法计算产量的实例。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Yield estimation of VLSI circuits with downscaled layouts

This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find a scaling factor of the IC design which is optimal from the manufacturing yield point of view. It also allows us to reduce time-consuming extraction of the critical area functions. Examples of yield calculations using the proposed method are presented as well.

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Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

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