Bandwidth optimization of CMOS two-stage operational amplifiers under power consumption and area constraints

This paper studies the design of standard CMOS two-stage operational amplifiers under power consumption and area constraints. The focus of the work is unity-gain bandwidth optimization, which is achieved by means of a procedure based on numerical analysis that allows determining the optimum sizing of op-amp transistors and the compensation capacitance as well as the best splitting of the allowed bias current between the two stages. The paper also provides a simplified algebraic solution for the case of large capacitive loads. The results from the proposed optimization procedure are compared to circuit simulation.