K. Matsuura, J. Shimizu, Mayato Toyama, T. Ohashi, I. Muneta, S. Ishihara, K. Kakushima, K. Tsutsui, A. Ogura, H. Wakabayashi
{"title":"用Al2O3薄膜和TiN顶栅钝化溅射沉积mos2薄沟道的芯片级集成非misfet","authors":"K. Matsuura, J. Shimizu, Mayato Toyama, T. Ohashi, I. Muneta, S. Ishihara, K. Kakushima, K. Tsutsui, A. Ogura, H. Wakabayashi","doi":"10.1109/EDTM.2018.8421491","DOIUrl":null,"url":null,"abstract":"We have fabricated a chip-level-integrated top-gate n MISFET with sputter-deposited-MoS<inf>2</inf> film and confirmed n-type operation. A sputtering method enabled us to form a large-scale MoS<inf>2</inf> thin film followed by H2S annealing to compensate sulfur vacancies. Two passivation films of ALD-Al<inf>2</inf>O<inf>3</inf> enhanced the process endurance of MoS<inf>2</inf> channel. Therefore, we realized TiN-top-gate n MISFETs and this process is a substantial first step to realize industrial chip-level LSIs with MoS<inf>2</inf>-channel FETs.","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Chip-Level-Integrated nMISFETs with Sputter-Deposited-MoS2 Thin Channel Passivated by Al2O3 Film and TiN Top Gate\",\"authors\":\"K. Matsuura, J. Shimizu, Mayato Toyama, T. Ohashi, I. Muneta, S. Ishihara, K. Kakushima, K. Tsutsui, A. Ogura, H. Wakabayashi\",\"doi\":\"10.1109/EDTM.2018.8421491\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have fabricated a chip-level-integrated top-gate n MISFET with sputter-deposited-MoS<inf>2</inf> film and confirmed n-type operation. A sputtering method enabled us to form a large-scale MoS<inf>2</inf> thin film followed by H2S annealing to compensate sulfur vacancies. Two passivation films of ALD-Al<inf>2</inf>O<inf>3</inf> enhanced the process endurance of MoS<inf>2</inf> channel. Therefore, we realized TiN-top-gate n MISFETs and this process is a substantial first step to realize industrial chip-level LSIs with MoS<inf>2</inf>-channel FETs.\",\"PeriodicalId\":418495,\"journal\":{\"name\":\"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTM.2018.8421491\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTM.2018.8421491","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Chip-Level-Integrated nMISFETs with Sputter-Deposited-MoS2 Thin Channel Passivated by Al2O3 Film and TiN Top Gate
We have fabricated a chip-level-integrated top-gate n MISFET with sputter-deposited-MoS2 film and confirmed n-type operation. A sputtering method enabled us to form a large-scale MoS2 thin film followed by H2S annealing to compensate sulfur vacancies. Two passivation films of ALD-Al2O3 enhanced the process endurance of MoS2 channel. Therefore, we realized TiN-top-gate n MISFETs and this process is a substantial first step to realize industrial chip-level LSIs with MoS2-channel FETs.