一种新的CMOS逻辑兼容1T-CRRAM制造方法

2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2016-04-25 DOI:10.1109/VLSI-TSA.2016.7480498

Hung-Yu Chen, H. Chen, Y. Kao, Ping-Yu Chen, Y. King, C. Lin

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引用次数: 3

摘要

本研究提出了一种在先进的90纳米CMOS逻辑工艺中提高CRRAM成品率的新方法。提出了采用接触式蚀刻工艺控制厚度和尺寸的方法来制造原CMOS兼容的CRRAM。由于接触孔蚀刻在不同的ILD拓扑结构上的差异，剩余的RRAM的TMO可能导致存储阵列的均匀性和良率问题。为了减少生产变化，本文首次提出并论证了一种新的接触式RRAM工艺。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A new manufacturing method of CMOS logic compatible 1T-CRRAM

This study proposed a new manufacturing method for improving the fabrication yield of CRRAM in advanced 90nm CMOS logic process. The original CMOS compatible CRRAM is proposed to fabricate by the thickness and size control of contact etch process. Due to the variation of contact hole etch on different ILD topographies, the remained RRAM's TMO could result in uniformity and yield problems of memory arrays. In order to decline the production variation, a new refilling Contact RRAM process is firstly proposed and demonstrated in this paper.

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2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

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