Xuemei Liu, L. Pan, X. Zhao, Fengying Qiao, Dong Wu, Jun Xu
{"title":"一种新型的软误差免疫SRAM单元","authors":"Xuemei Liu, L. Pan, X. Zhao, Fengying Qiao, Dong Wu, Jun Xu","doi":"10.1109/IIRW.2013.6804187","DOIUrl":null,"url":null,"abstract":"The scaling down of the technology node makes integrated circuits more susceptible to soft errors, normally caused by radiation strike. In this paper, we propose a novel Soft Error Immunity (SEI) SRAM cell using a standard 65nm CMOS process, which has good tolerance to soft errors, especially at read state. SPICE simulation results show that the proposed cell is robust to the variation of process, voltage and temperature. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed cell can recover the upset-state.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A novel soft error immunity SRAM cell\",\"authors\":\"Xuemei Liu, L. Pan, X. Zhao, Fengying Qiao, Dong Wu, Jun Xu\",\"doi\":\"10.1109/IIRW.2013.6804187\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The scaling down of the technology node makes integrated circuits more susceptible to soft errors, normally caused by radiation strike. In this paper, we propose a novel Soft Error Immunity (SEI) SRAM cell using a standard 65nm CMOS process, which has good tolerance to soft errors, especially at read state. SPICE simulation results show that the proposed cell is robust to the variation of process, voltage and temperature. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed cell can recover the upset-state.\",\"PeriodicalId\":287904,\"journal\":{\"name\":\"2013 IEEE International Integrated Reliability Workshop Final Report\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Integrated Reliability Workshop Final Report\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2013.6804187\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Integrated Reliability Workshop Final Report","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2013.6804187","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The scaling down of the technology node makes integrated circuits more susceptible to soft errors, normally caused by radiation strike. In this paper, we propose a novel Soft Error Immunity (SEI) SRAM cell using a standard 65nm CMOS process, which has good tolerance to soft errors, especially at read state. SPICE simulation results show that the proposed cell is robust to the variation of process, voltage and temperature. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed cell can recover the upset-state.
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