First Demonstration of Top-Gated ITO Transistors: Effect of Channel Passivation

Ultrathin indium tin oxide (ITO) transistors have shown good performance, with effective mobility $\mu_{\text{eff}}\sim 55\text{cm}^{2}\mathrm{V}^{-1}\mathrm{s}^{-1}$ [1]. Due to their wide band gap (>3 eV), low-temperature large-area deposition, low off- and high on-state current, they are promising candidates for back-end of the line (BEOL) and 3D integration [1], [2]. However, all ITO transistors to date have back-gated (BG) structures, and the effect of top dielectrics or capping layers is unknown. Here, we demonstrate the first top-gated (TG) ITO transistors while successfully passivating the channel during TG dielectric layer deposition. We compare different precursors for atomic layer deposition (ALD) of the passivation layer and their role on device behavior. Ozone-based ALD minimizes the negative shift in threshold voltage $(V_{\mathrm{T}})$ at short channel lengths and achieves $I_{\max}\approx 260\mu \mathrm{A}/\mu \mathrm{m}$ at VDS =1 V, on/off current ratio of $\sim 10^{10}$ for $L\approx 700$ nm channel. Our TG ITO transistors have $\mu_{\text{eff}}\approx 60\text{cm}^{2}\mathrm{V}^{-1}\mathrm{s}^{-1}$.