{"title":"用于4½的双极单片模拟子系统;数字A/D转换器","authors":"K. Hareyama, K. Yoshimura, K. Murase","doi":"10.1109/ISSCC.1977.1155623","DOIUrl":null,"url":null,"abstract":"A HIGHLY ACCURATE A/D convcrter has been required in data handling systems for a microprocessor and in digital multimeters. Responding to this recent demand, a CMOS monolithic structure has been widely employed in combination with the dual slope technique’ 7’. The CMOS process, however, places a limitation on the resolution of an A(D converter at 3% digits. In the dual slope technique, on the other hand, a feedback loop is constructed between the analog and the digital subsystems. This arrangement degrades the electrical isolation between the two systems.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A bipolar monolithic analog subsystem for a 4½ digit A/D converter\",\"authors\":\"K. Hareyama, K. Yoshimura, K. Murase\",\"doi\":\"10.1109/ISSCC.1977.1155623\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A HIGHLY ACCURATE A/D convcrter has been required in data handling systems for a microprocessor and in digital multimeters. Responding to this recent demand, a CMOS monolithic structure has been widely employed in combination with the dual slope technique’ 7’. The CMOS process, however, places a limitation on the resolution of an A(D converter at 3% digits. In the dual slope technique, on the other hand, a feedback loop is constructed between the analog and the digital subsystems. This arrangement degrades the electrical isolation between the two systems.\",\"PeriodicalId\":416313,\"journal\":{\"name\":\"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1977.1155623\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1977.1155623","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A bipolar monolithic analog subsystem for a 4½ digit A/D converter
A HIGHLY ACCURATE A/D convcrter has been required in data handling systems for a microprocessor and in digital multimeters. Responding to this recent demand, a CMOS monolithic structure has been widely employed in combination with the dual slope technique’ 7’. The CMOS process, however, places a limitation on the resolution of an A(D converter at 3% digits. In the dual slope technique, on the other hand, a feedback loop is constructed between the analog and the digital subsystems. This arrangement degrades the electrical isolation between the two systems.