{"title":"低功耗高性能0.25-/spl mu/m先进PNP双极工艺的设计与优化","authors":"B. Djezzar","doi":"10.1109/SMICND.1996.557309","DOIUrl":null,"url":null,"abstract":"Low-power and very-high-performance 0.25-/spl mu/m vertical PNP bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This PNP transistor has a 25-nm-wide emitter, a 38-nm-wide base region, a current gain of 17 (without poly-Si emitter effect), and maximum cut-off frequency of 24-GHz. The conventional ECL circuits, designed by this PNP transistor, exhibit an unloaded gate delay of 22-ps at 1.75-mW, and a delay time less than 16-ps/stage for unloaded ECL ring-oscillator.","PeriodicalId":266178,"journal":{"name":"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and optimization of a low-power and very-high-performance 0.25-/spl mu/m advanced PNP bipolar process\",\"authors\":\"B. Djezzar\",\"doi\":\"10.1109/SMICND.1996.557309\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Low-power and very-high-performance 0.25-/spl mu/m vertical PNP bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This PNP transistor has a 25-nm-wide emitter, a 38-nm-wide base region, a current gain of 17 (without poly-Si emitter effect), and maximum cut-off frequency of 24-GHz. The conventional ECL circuits, designed by this PNP transistor, exhibit an unloaded gate delay of 22-ps at 1.75-mW, and a delay time less than 16-ps/stage for unloaded ECL ring-oscillator.\",\"PeriodicalId\":266178,\"journal\":{\"name\":\"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMICND.1996.557309\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.1996.557309","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and optimization of a low-power and very-high-performance 0.25-/spl mu/m advanced PNP bipolar process
Low-power and very-high-performance 0.25-/spl mu/m vertical PNP bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This PNP transistor has a 25-nm-wide emitter, a 38-nm-wide base region, a current gain of 17 (without poly-Si emitter effect), and maximum cut-off frequency of 24-GHz. The conventional ECL circuits, designed by this PNP transistor, exhibit an unloaded gate delay of 22-ps at 1.75-mW, and a delay time less than 16-ps/stage for unloaded ECL ring-oscillator.
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