The Impact of Heterogeneity on a Reconfigurable Multicore System

Modern embedded system must efficiently exploit parallelism at thread-and instruction-level to achieve the best performance with the lowest energy consumption possible. While Multiprocessor System-on-Chip (MPSoCs) are a commonly used solution, they do not provide an effective environment for software production, as each processing element implements a different Instruction Set Architecture (ISA). On the other hand, processors such as the ARM big.LITTLE comprise multicores with different organizations and the same ISA. However, such cores are power consuming superscalar microarchitectures. Dynamic Reconfigurable Architectures (DRA) emerge as a solution to fill this gap. By taking advantage of its regular fabric, it is possible to develop a low-energy heterogeneous system by coupling to the cores DRAs with different processing capabilities and that implements the same ISA. In this work, we evaluate such system, varying both the size of the DRAs and the memory system involved. We show that, by tuning the latter, one can reach energy savings of up to 36%, while by using a fully heterogeneous system, saves of 28% in energy and losses of 7% in performance are observed when compared to its counterpart homogeneous version.