采用10nm FinFET技术的690mV 4.4Gbps/引脚全数字LPDDR4 PHY

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI:10.1109/ESSCIRC.2016.7598341

Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyun‐Ho Kim, H. Yi, Y. Nam, J.I. Choi, Sanghune Park, Sanghyun Lee

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引用次数: 3

摘要

本文提出了一种采用10nm FinFET工艺技术，采用位片结构的4.4Gbps/引脚全数字LPDDR4 PHY。提出的位片结构包括新的I/O结构，可在不降低片外性能的情况下减少面积，并具有数字调差能力，可最大化有效窗口余量，从而有助于存储器接口系统的低电压操作。采用10nm FinFET技术的测试芯片在690mV下具有稳定的4.4Gbps内存访问和112ps有效窗口裕度(49% UI)。实现的16位LPDDR4 PHY仅占用0.57 mm2(包括一个锁相环)。

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A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology

This paper presents a 4.4Gbps/pin all-digital LPDDR4 PHY with a bit-slice architecture in 10nm FinFET process technology. The proposed bit-slice architecture includes new I/O structure for area reduction without any off-chip performance degradation and digital duty-tuning capability to maximize the valid window margin, which contributes to low voltage operation in memory interface system. The test chip in 10nm FinFET technology demonstrated stable 4.4Gbps memory access with 112ps valid window margin (49% UI) at 690mV. The implemented 16-bit LPDDR4 PHY occupies only 0.57 mm2 including a PLL.

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ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference

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