一种新的组态电路结构,可加速部分可重构器件的重配置和重定位

T. Marconi, J. Hur, K. Bertels, G. Gaydadjiev
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引用次数: 8

摘要

长重构时间是动态可重构系统的主要瓶颈。已经提出了许多方法来解决这个问题。但是,通常不会考虑引入这种开销的配置电路的改进。高重新配置时间是由于通过受限数据路径发送的大量配置位。为了缓解这个问题,我们提出了一种新的FPGA配置电路架构来加速比特流(重)配置和重定位。使用MCNC基准集的实验结果表明,与最先进的方法相比,我们的提议的重新配置速度快4倍,重新定位效率高19.8倍。这是通过在飞行中只传输配置所需的数据和在重新定位时避免外部通信来实现的。此外,评估基准的配置比特流大小平均减少了65%。此外,我们的建议引入了可以忽略不计的硬件和通信协议开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices
Long reconfiguration times form a major bottleneck in dynamic reconfigurable systems. Many approaches have been proposed to address this problem. However, improvements in the configuration circuit that introduces this overhead are usually not considered. The high reconfiguration times are due to the large amount of configuration bits sent through a constrained data path. In order to alleviate this, we propose a novel FPGA configuration circuit architecture to speedup bitstream (re)configuration and relocation. Experimental results using the MCNC benchmark set indicate that our proposal reconfigures 4 times faster and relocates 19.8 times more efficient compared to the state of the art approaches. This is achieved by transporting only the data required for the configuration in flight and by avoiding external communication while relocating. Moreover, the configuration bitstream sizes of the evaluated benchmarks are reduced by 65%on average. In addition, our proposal introduces negligible hardware and communication protocol overheads.
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