An all-digital PLL with SAR frequency locking system in 65nm SOTB CMOS

This paper presents an all-digital PLL (ADPLL) which synthesizes any frequency using the successive approximation (SAR) algorithm. The proposed ADPLL consists of a high-frequency resolution digitally controlled oscillator, a time-to-digital converter, a frequency detection divider and the SAR controller. The proposed ADPLL is designed using 65nm SOTB CMOS process and occupies an area of 124.6×68.4μm2. The range of output frequency is from 577 to 1876MHz at 1.0V power supply. The power consumption is 0.46mW at 1876MHz. The number of clocks to lock-in is 10 clocks in the best case and 34 clocks in the typical cases.