Design and VLSI Implementation of Interpolators/Decimators for DUC/DDC

In this paper, we implemented a DUC/DDC for DSBSC modulation technique, which is used for power line communication system. The input signal is ranging from 300-4000 Hz is sampled at 64 KHz is fed to the series of two stage CIC interpolation filters. A CIC filters up-samples the input signal by a factor 12. The up-sampled signal is now given to the multiplier as the first input. Variable DDS is used to generate HF carrier frequencies in the range of 20-512 KHz is given as a second input to the multiplier will produce the DUC signal. Here 48 KHz carrier is selected. This DUC output is given as an input for DDC. In DDC, the incoming signal is multiplied with DDS which generates frequency of same as in DUC. The output of the multiplier is down-sampled by factor 12 by two stage CIC decimation FIR filter. The input signal of DUC and the output of DDC are compared. These filters are designed using Matlab simulink and developed Verilog code. Simulation is performed using ModelSim XE 6.3c and functional verification is carried out using Xilinx ISE 10.1 and FPGA implementation on Spartan-3. Here our main aim is to implement both DUC and DDC in a single FPGA. Integrating both blocks in same IC such a way that it has to perform both down conversion and up conversion. This is designed for reduce the power consumption of the blocks and also to reduce the cost. The design used 23% of flip-flop’s, 20% of look up tables, 30% of slices out of total available in Spartan-3 FPGA board. Design used minimum 10.184ns period of clock and minimum input arrival time before clock is 8.568ns and Maximum output required time after clock is 6.216ns. The maximum operating frequency of the design is 98.191MHz. The total power consumed by the design is 42mW at 26.30C.