纳米级SOI技术超低漏电电路优化设计新策略及分析

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI:10.1109/LPE.2003.1231855

K. Das, R. Joshi, C. Chuang, P. Cook, Richard B. Brown

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引用次数: 6

摘要

本文提出了同时减少待机栅极和亚阈值泄漏的新型SOI电路策略。分析了各种增强型MTCMOS设计方案。提出了一种新的头脚晶体管V/sub / TH和尺寸分配方法，并对头脚晶体管的堆叠进行了分析。确定了各种设计约束条件下的最佳堆垛高度和锥形/浆料比。我们的策略将MTCMOS待机泄漏进一步降低了20倍，并将虚拟电源噪声降低了15%。

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New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology

This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed. A new method for assigning the V/sub TH/ and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed. The optimum stacking height and tapering/sizing ratio under various design constraints are determined. Our strategies reduce MTCMOS standby leakage further by as much as 20/spl times/ and reduce virtual supply noise by 15%.

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来源期刊

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

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