每秒40千兆比特的ATM交换机的架构与设计

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI:10.1109/ICCD.1995.528833

S. Butner, David A. Skirmont

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引用次数: 10

摘要

本文介绍了一种高性能4输入4输出异步传输模式(ATM)交换机的架构，该交换机是美国国防部高级研究计划署(arpa)资助的加州大学圣巴巴拉分校“雷电”项目的一部分。该研究项目的重点是ATM链路和交换机的设计和原型演示，每条TDM链路的运行速度为每秒40千兆位或以上，具有100gbps的潜在可扩展性。这种激进的链路速率对交换机架构提出了严格的要求，特别是缓冲方案。本文介绍了ATM交换机的结构，并对主要的设计选择进行了论证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Architecture and design of a 40 gigabit per second ATM switch

This paper presents the architecture of a very high performance 4-input, 4-output asynchronous transfer mode (ATM) switch that has been designed as part of the ARPA-sponsored "Thunder and Lightning" project at the University of California, Santa Barbara. This research project is focused on the design and prototype demonstration of ATM links and switches operating at or above 40 gigabits per second per TDM link, with potential scalability to 100 Gbps. Such aggressive link rates place severe requirements on switch architecture, particularly the buffering scheme. In this paper we present the ATM switch structure and justify the main design choices.

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Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors

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