带有片上ECC的64Kb CMOS EEROM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156662

S. Mehrotra, Tsung-Ching Wu, Te-Long Chiu, G. Perlegos

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引用次数: 5

摘要

采用1.5μm n阱CMOS on epi技术的5V-only 64Kb EEROM，具有85μ m22的双晶体管电池和33100 mil2的芯片面积。地址边缘检测电路技术在50mW有功功耗下实现了100ns的典型访问时间。

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A 64Kb CMOS EEROM with on-chip ECC

A 5V-only 64Kb EEROM using a 1.5μm N-well CMOS on epi technology, and featuring a 85μm²two-transistor cell and 33100 mil²die area, will be reported. Address edge detection circuit techniques have resulted in a 100ns typical access time at 50mW active power dissipation.

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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