Tong Liu, Yuanming Zhu, Anil Korkmaz, S. Delshadpour, S. Palermo
{"title":"基于130nm SiGe BiCMOS的40Gb/s多频带均衡线性重驱动器","authors":"Tong Liu, Yuanming Zhu, Anil Korkmaz, S. Delshadpour, S. Palermo","doi":"10.1109/BCICTS50416.2021.9682495","DOIUrl":null,"url":null,"abstract":"A linear redriver circuit implements multi-band equalization techniques to efficiently compensate for high-frequency channel loss and extend high-speed wireline link reach. Input and output stage emitter-follower buffers with dual AC and DC paths provide programmable low-frequency peaking for channel skin effect, while a continuous-time linear equalizer (CTLE) utilizes RC degeneration in the input stage for mid-band peaking and a subsequent feedback structure contributes to additional high-frequency peaking to compensate for the additional dielectric loss effects. A variable-gain amplifier (VGA) stage provides up to 7.1dB tunable gain and utilizes negative capacitive loads for bandwidth extension. Input and output return loss of −11.0dB and −12.2dB is respectively achieved at 20GHz with input and output T-coil stages that distribute the ESD circuitry capacitance. Fabricated in a 130nm SiGe BiCMOS process, the redriver achieves 23.5dB max peaking at 20GHz and supports a 1Vppd linear output swing. Per-channel power consumption is 115.2mW from a 1.8V supply.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 40Gb/s Linear Redriver with Multi-Band Equalization in 130nm SiGe BiCMOS\",\"authors\":\"Tong Liu, Yuanming Zhu, Anil Korkmaz, S. Delshadpour, S. Palermo\",\"doi\":\"10.1109/BCICTS50416.2021.9682495\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A linear redriver circuit implements multi-band equalization techniques to efficiently compensate for high-frequency channel loss and extend high-speed wireline link reach. Input and output stage emitter-follower buffers with dual AC and DC paths provide programmable low-frequency peaking for channel skin effect, while a continuous-time linear equalizer (CTLE) utilizes RC degeneration in the input stage for mid-band peaking and a subsequent feedback structure contributes to additional high-frequency peaking to compensate for the additional dielectric loss effects. A variable-gain amplifier (VGA) stage provides up to 7.1dB tunable gain and utilizes negative capacitive loads for bandwidth extension. Input and output return loss of −11.0dB and −12.2dB is respectively achieved at 20GHz with input and output T-coil stages that distribute the ESD circuitry capacitance. Fabricated in a 130nm SiGe BiCMOS process, the redriver achieves 23.5dB max peaking at 20GHz and supports a 1Vppd linear output swing. Per-channel power consumption is 115.2mW from a 1.8V supply.\",\"PeriodicalId\":284660,\"journal\":{\"name\":\"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)\",\"volume\":\"81 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BCICTS50416.2021.9682495\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS50416.2021.9682495","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 40Gb/s Linear Redriver with Multi-Band Equalization in 130nm SiGe BiCMOS
A linear redriver circuit implements multi-band equalization techniques to efficiently compensate for high-frequency channel loss and extend high-speed wireline link reach. Input and output stage emitter-follower buffers with dual AC and DC paths provide programmable low-frequency peaking for channel skin effect, while a continuous-time linear equalizer (CTLE) utilizes RC degeneration in the input stage for mid-band peaking and a subsequent feedback structure contributes to additional high-frequency peaking to compensate for the additional dielectric loss effects. A variable-gain amplifier (VGA) stage provides up to 7.1dB tunable gain and utilizes negative capacitive loads for bandwidth extension. Input and output return loss of −11.0dB and −12.2dB is respectively achieved at 20GHz with input and output T-coil stages that distribute the ESD circuitry capacitance. Fabricated in a 130nm SiGe BiCMOS process, the redriver achieves 23.5dB max peaking at 20GHz and supports a 1Vppd linear output swing. Per-channel power consumption is 115.2mW from a 1.8V supply.