用于强耦合互连的高性能总线体系结构

Michael N. Skoufis, Kedar Karmarkar, T. Haniotakis, S. Tragoudas
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引用次数: 1

摘要

互连织物上的耦合和增加的导线电阻破坏了瞬态电信号的速度。减少串扰设计的强力方法依赖于增加相互之间的互连距离和使用额外的重复逻辑。提出了一种利用现有电噪声的流水线总线结构。在分析中考虑了工艺变化。该技术在不同长度的65 nm和90 nm CMOS工艺中进行了验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A High-Performance Bus Architecture for Strongly Coupled Interconnects
Coupling and increasing wire resistance on interconnect fabrics undermine the speed of the transient electrical signals. A brute-force approach for a crosstalk-reduced design relies on increasing the distance of interconnects from each other and using additional repeated logic. A pipelined bus-architecture exploiting the existing electrical noise is proposed. Process variations are taken into consideration in the analysis. The proposed technique is validated for the 65 nm and 90 nm CMOS processes for interconnects of various lengths.
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