{"title":"晶圆片背面涂布的网版和网版印刷工艺","authors":"M. Whitmore, J. Schake","doi":"10.1109/IEMT.2008.5507863","DOIUrl":null,"url":null,"abstract":"Stencil printing equipment has traditionally been used in the surface mount assembly industry for solder paste printing. In recent years the flexibility of the tool has been exploited for a wide range of materials and processes to aid semiconductor packaging and assembly. One such application has been the deposition of adhesive coatings onto the backside of silicon wafers. This paper looks at the application of two totally different epoxy materials to the non active side of silicon wafers one providing a B-stageble die attach layer and one providing a protective laser-markable cover layer aimed at protecting individual die from damage during dicing. Printing trials, with the two commercially standard, non-conductive epoxy based materials were conducted. For each material, 24 200mm wafers were printed. Both screen and stencil printing processes were compared for each material. Effects of printing process parameters were also considered. Coating thickness planarity across a wafer is the key metric for a successful coating process. For each wafer processed a minimum of 16 thickness measurements were made. Results showing thickness control capability are presented. The study demonstrates that coating co-planarity accomplishing ±12.5μm @ 6 sigma control with cured thickness's down to 30μm is possible.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Screen and stencil printing processes for wafer backside coating\",\"authors\":\"M. Whitmore, J. Schake\",\"doi\":\"10.1109/IEMT.2008.5507863\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Stencil printing equipment has traditionally been used in the surface mount assembly industry for solder paste printing. In recent years the flexibility of the tool has been exploited for a wide range of materials and processes to aid semiconductor packaging and assembly. One such application has been the deposition of adhesive coatings onto the backside of silicon wafers. This paper looks at the application of two totally different epoxy materials to the non active side of silicon wafers one providing a B-stageble die attach layer and one providing a protective laser-markable cover layer aimed at protecting individual die from damage during dicing. Printing trials, with the two commercially standard, non-conductive epoxy based materials were conducted. For each material, 24 200mm wafers were printed. Both screen and stencil printing processes were compared for each material. Effects of printing process parameters were also considered. Coating thickness planarity across a wafer is the key metric for a successful coating process. For each wafer processed a minimum of 16 thickness measurements were made. Results showing thickness control capability are presented. The study demonstrates that coating co-planarity accomplishing ±12.5μm @ 6 sigma control with cured thickness's down to 30μm is possible.\",\"PeriodicalId\":151085,\"journal\":{\"name\":\"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)\",\"volume\":\"80 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.2008.5507863\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.2008.5507863","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Screen and stencil printing processes for wafer backside coating
Stencil printing equipment has traditionally been used in the surface mount assembly industry for solder paste printing. In recent years the flexibility of the tool has been exploited for a wide range of materials and processes to aid semiconductor packaging and assembly. One such application has been the deposition of adhesive coatings onto the backside of silicon wafers. This paper looks at the application of two totally different epoxy materials to the non active side of silicon wafers one providing a B-stageble die attach layer and one providing a protective laser-markable cover layer aimed at protecting individual die from damage during dicing. Printing trials, with the two commercially standard, non-conductive epoxy based materials were conducted. For each material, 24 200mm wafers were printed. Both screen and stencil printing processes were compared for each material. Effects of printing process parameters were also considered. Coating thickness planarity across a wafer is the key metric for a successful coating process. For each wafer processed a minimum of 16 thickness measurements were made. Results showing thickness control capability are presented. The study demonstrates that coating co-planarity accomplishing ±12.5μm @ 6 sigma control with cured thickness's down to 30μm is possible.