负电容型无掺杂纳米管隧道场效应晶体管的设计与研究

IF 1 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Apoorva, Naveen Kumar, S. Intekhab Amin, Sunny Anand
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引用次数: 2

摘要

采用锆钛酸铅(PZT)栅极堆诱导负电容,对铁电材料基无掺杂纳米管隧道场效应晶体管进行了研究和分析。采用朗道-卡拉特尼科夫方程推导铁电材料的参数值,保证了计算结果的准确性。隧道场效应晶体管的纳米管结构由于其栅极全方位结构,使得其具有更好的静电控制能力。负电容的加入进一步降低了该结构的电压供应要求和功耗,同时改善了开关性能。此外,还研究了该器件对不同厚度介电PZT材料的影响。计算出所研究器件的阈值电压为0.281 V,器件的平均亚阈值斜率降至18.271 mV/ 10年,远低于60 mV/ 10年的热离子极限。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Design and investigation of negative capacitance–based core-shell dopingless nanotube tunnel field-effect transistor

Design and investigation of negative capacitance–based core-shell dopingless nanotube tunnel field-effect transistor

Investigation and analysis of a ferroelectric material–based dopingless nanotube tunnel field-effect transistor are conducted using a lead zirconate titanate (PZT) gate stack to induce negative capacitance in the device. Landau–Khalatnikov equations are used in deriving the parameter values of the ferroelectric material to ensure accurate results. The nanotube structure of the tunnel field-effect transistor allows for better electrostatic control owing to its gate-all-around structure. Incorporation of negative capacitance further reduces the voltage supply requirement and power consumption of the structure while simultaneously improving switching. In addition, the device is studied for varying thicknesses of the dielectric PZT material. The threshold voltage of the device under study was calculated as 0.281 V, and the average subthreshold slope of the device was reduced to 18.271 mV/decade, far below the thermionic limit of 60 mV/decade.

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来源期刊
Iet Circuits Devices & Systems
Iet Circuits Devices & Systems 工程技术-工程:电子与电气
CiteScore
3.80
自引率
7.70%
发文量
32
审稿时长
3 months
期刊介绍: IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers
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