用于嵌入式MP3解码器的低功耗DSP核心

IECON'01. 27th Annual Conference of the IEEE Industrial Electronics Society (Cat. No.37243) Pub Date : 2001-11-29 DOI:10.1109/IECON.2001.975579

Dishi Lai, Q. Lin, Sizhong Chen, M. Margala

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引用次数: 2

摘要

提出了一种用于MPEG1音频三层(Audio Layer III, MP3)解码器的低功耗32位20 MIPS DSP内核。它有一个专门为实现MP3解码算法而设计的体系结构。除了其他有效的动态电源管理方案外，作者还使用指令级时钟门控技术来实现便携式应用的低功耗。采用0.25 /spl mu/m, 2.5 V CMOS工艺。

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A low power DSP core for an embedded MP3 decoder

A low power 32-bit 20 MIPS DSP core designed for MPEG1 Audio Layer III (MP3) decoder is proposed. It has an architecture designed specifically for MP3 decoding algorithm implementation. The authors used the instruction level clock gating technique to achieve lower power for portable applications besides other effective dynamic power management schemes. A 0.25 /spl mu/m, 2.5 V CMOS process was used.

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IECON'01. 27th Annual Conference of the IEEE Industrial Electronics Society (Cat. No.37243)

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