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用于12b A/D应用的锁存比较器

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1980.1156135
G. Erdi
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引用次数: 0

摘要

将描述一种误差为0.1LSB、响应时间为50ns、过载0.5LSB的比较器，用于12b连续近似A/D。隔离的电路结包括一个埋式齐纳电平移位。
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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A latching comparator for 12b A/D applications
A comparator with 0.1LSB error and 50ns response time with 0.5LSB overdrive, for use in a 12b successive approximation A/D will be described. The circuit-junction isolated-includes a buried-zener level shift.
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1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
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