Datapath library reuse in the design of a high performance floating point unit

This paper describes the use of a datapath library in the design of a high performance, pipelined floating point unit (FPU) macrocell. The existence of the intellectual property (IP) library allowed the rapid completion of the FPU within the context of a high performance structured custom design flow. The 165000 transistor floating point unit was completed in 25 man months from initial customer specification to final physical assembly. The macrocell occupies 2.45 mm/spl times/2.55 mm in a 0.35 /spl mu/m, 4 metal CMOS process and has a simulated cycle time of 5.2 ns at 3.3 V and 85/spl deg/C.