{"title":"故障恢复中统一潮流控制器与谐波滤波器的组合方式","authors":"J. Dejvises, T. Green","doi":"10.1109/ICPST.2000.897104","DOIUrl":null,"url":null,"abstract":"This paper addresses two issues in operation of a unified power flow controller (UPFC), enhancement of fault recovery and controller design accounting for filter dynamics. Performance of a UPFC is improved by a temporary modification of the UPFC into double static synchronous series compensator (SSSC) in order to double its capability in fault recovery mode. A battery is required as an energy source in the DC link of the double SSSC. The size of the battery for the SSSC has been be investigated. It was found that the double SSSC in fault recovery mode has almost twice the performance of the UPFC and the size of battery for the UPFC is reasonable for grid scale use. With the double SSSC in fault recovery mode, a combination control mode is suggested for the UPFC. One of the important parts of the UPFC is the filter at the output of the inverter. The function of the UPFC filter is to attenuate the harmonics generated by the inverter. In this paper a harmonic trap filter together with a low-pass filter are applied to the UPFC and investigated. Single-phase models are used to design cut-off frequencies whilst the d-q model is included in the UPFC controller design. It was found that if the filter dynamics are neglected in the control design, then the controllers response will be different. The test system used is a one-machine, two transmissions lines and an infinite busbar. All of the simulations were implemented using the EMTP. Additionally Matlab and Simulink programming environment were used to provide transfer function simulation for the controller design. The simulation results from both programs are compared.","PeriodicalId":330989,"journal":{"name":"PowerCon 2000. 2000 International Conference on Power System Technology. Proceedings (Cat. No.00EX409)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A combination mode for a unified power flow controller in fault recovery and with harmonic filter\",\"authors\":\"J. Dejvises, T. Green\",\"doi\":\"10.1109/ICPST.2000.897104\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper addresses two issues in operation of a unified power flow controller (UPFC), enhancement of fault recovery and controller design accounting for filter dynamics. Performance of a UPFC is improved by a temporary modification of the UPFC into double static synchronous series compensator (SSSC) in order to double its capability in fault recovery mode. A battery is required as an energy source in the DC link of the double SSSC. The size of the battery for the SSSC has been be investigated. It was found that the double SSSC in fault recovery mode has almost twice the performance of the UPFC and the size of battery for the UPFC is reasonable for grid scale use. With the double SSSC in fault recovery mode, a combination control mode is suggested for the UPFC. One of the important parts of the UPFC is the filter at the output of the inverter. The function of the UPFC filter is to attenuate the harmonics generated by the inverter. In this paper a harmonic trap filter together with a low-pass filter are applied to the UPFC and investigated. Single-phase models are used to design cut-off frequencies whilst the d-q model is included in the UPFC controller design. It was found that if the filter dynamics are neglected in the control design, then the controllers response will be different. The test system used is a one-machine, two transmissions lines and an infinite busbar. All of the simulations were implemented using the EMTP. Additionally Matlab and Simulink programming environment were used to provide transfer function simulation for the controller design. The simulation results from both programs are compared.\",\"PeriodicalId\":330989,\"journal\":{\"name\":\"PowerCon 2000. 2000 International Conference on Power System Technology. Proceedings (Cat. No.00EX409)\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-12-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"PowerCon 2000. 2000 International Conference on Power System Technology. Proceedings (Cat. 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A combination mode for a unified power flow controller in fault recovery and with harmonic filter
This paper addresses two issues in operation of a unified power flow controller (UPFC), enhancement of fault recovery and controller design accounting for filter dynamics. Performance of a UPFC is improved by a temporary modification of the UPFC into double static synchronous series compensator (SSSC) in order to double its capability in fault recovery mode. A battery is required as an energy source in the DC link of the double SSSC. The size of the battery for the SSSC has been be investigated. It was found that the double SSSC in fault recovery mode has almost twice the performance of the UPFC and the size of battery for the UPFC is reasonable for grid scale use. With the double SSSC in fault recovery mode, a combination control mode is suggested for the UPFC. One of the important parts of the UPFC is the filter at the output of the inverter. The function of the UPFC filter is to attenuate the harmonics generated by the inverter. In this paper a harmonic trap filter together with a low-pass filter are applied to the UPFC and investigated. Single-phase models are used to design cut-off frequencies whilst the d-q model is included in the UPFC controller design. It was found that if the filter dynamics are neglected in the control design, then the controllers response will be different. The test system used is a one-machine, two transmissions lines and an infinite busbar. All of the simulations were implemented using the EMTP. Additionally Matlab and Simulink programming environment were used to provide transfer function simulation for the controller design. The simulation results from both programs are compared.