{"title":"用于实时过程控制的VLSI模糊逻辑推理引擎","authors":"W. Dettloff, K. E. Yount","doi":"10.1109/CICC.1989.56741","DOIUrl":null,"url":null,"abstract":"The single-chip implementation of a general-purpose fuzzy logic inference engine is described. Features include a dynamically reconfigurable and cascadable architecture, TTL (transistor-transistor logic)-compatible host interface, laser-programmed redundancy, special mode for testability, RAM rule storage, and on-chip fuzzification and defuzzification. Up to 102 parallel rules can be processed in real-time control applications by utilizing a 1-μm, 3.3-V DLM CMOS technology. 580 KFLIPS (fuzzy logic inferences per second) are attained using 688 K transistors and 36-MHz operation","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"63 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":"{\"title\":\"A VLSI fuzzy logic inference engine for real-time process control\",\"authors\":\"W. Dettloff, K. E. Yount\",\"doi\":\"10.1109/CICC.1989.56741\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The single-chip implementation of a general-purpose fuzzy logic inference engine is described. Features include a dynamically reconfigurable and cascadable architecture, TTL (transistor-transistor logic)-compatible host interface, laser-programmed redundancy, special mode for testability, RAM rule storage, and on-chip fuzzification and defuzzification. Up to 102 parallel rules can be processed in real-time control applications by utilizing a 1-μm, 3.3-V DLM CMOS technology. 580 KFLIPS (fuzzy logic inferences per second) are attained using 688 K transistors and 36-MHz operation\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"63 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"35\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56741\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56741","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 35
摘要
介绍了一种通用模糊逻辑推理引擎的单片机实现。功能包括动态可重构和可级联架构，TTL(晶体管-晶体管逻辑)兼容的主机接口，激光编程冗余，可测试性的特殊模式，RAM规则存储，以及片上模糊化和去模糊化。采用1 μm、3.3 v DLM CMOS技术，可在实时控制应用中处理多达102条并行规则。580 KFLIPS(每秒模糊逻辑推理)使用688 K晶体管和36 mhz操作
A VLSI fuzzy logic inference engine for real-time process control
The single-chip implementation of a general-purpose fuzzy logic inference engine is described. Features include a dynamically reconfigurable and cascadable architecture, TTL (transistor-transistor logic)-compatible host interface, laser-programmed redundancy, special mode for testability, RAM rule storage, and on-chip fuzzification and defuzzification. Up to 102 parallel rules can be processed in real-time control applications by utilizing a 1-μm, 3.3-V DLM CMOS technology. 580 KFLIPS (fuzzy logic inferences per second) are attained using 688 K transistors and 36-MHz operation
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