{"title":"铜互连中的TDDB芯片可靠性","authors":"M. Bashir, Daehyun Kim, S. Lim, L. Milor","doi":"10.1109/IIRW.2010.5706503","DOIUrl":null,"url":null,"abstract":"Backend time dependent dielectric breakdown (TDDB) degrades the reliability of circuits with copper interconnects. We use test data to develop a methodology to evaluate chip lifetimes, because of backend TDDB, from layout statistics. We identify features in a layout that are critical to backend reliability, present a model to incorporate those features in determining chip lifetimes, and study the effect of different layout optimizations on chip lifetime.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"TDDB chip reliability in copper interconnects\",\"authors\":\"M. Bashir, Daehyun Kim, S. Lim, L. Milor\",\"doi\":\"10.1109/IIRW.2010.5706503\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Backend time dependent dielectric breakdown (TDDB) degrades the reliability of circuits with copper interconnects. We use test data to develop a methodology to evaluate chip lifetimes, because of backend TDDB, from layout statistics. We identify features in a layout that are critical to backend reliability, present a model to incorporate those features in determining chip lifetimes, and study the effect of different layout optimizations on chip lifetime.\",\"PeriodicalId\":332664,\"journal\":{\"name\":\"2010 IEEE International Integrated Reliability Workshop Final Report\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Integrated Reliability Workshop Final Report\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2010.5706503\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Integrated Reliability Workshop Final Report","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2010.5706503","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Backend time dependent dielectric breakdown (TDDB) degrades the reliability of circuits with copper interconnects. We use test data to develop a methodology to evaluate chip lifetimes, because of backend TDDB, from layout statistics. We identify features in a layout that are critical to backend reliability, present a model to incorporate those features in determining chip lifetimes, and study the effect of different layout optimizations on chip lifetime.
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