{"title":"具有线性锁相环的SiGe时钟和数据恢复IC,适用于10gb /s SONET应用","authors":"Y. Greshishchev, P. Schvan","doi":"10.1109/BIPOL.1999.803552","DOIUrl":null,"url":null,"abstract":"An integrated 10 Gb/s clock and data recovery circuit implemented in IBM's SiGe technology is presented. It employs a linear type PLL based on a single-edge version of the Hogge type phase detector, an LC-VCO and a high-performance charge pump. Measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with -5 V power supply.","PeriodicalId":194523,"journal":{"name":"Proceedings of the 1999 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.99CH37024)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"SiGe clock and data recovery IC with linear type PLL for 10 Gb/s SONET application\",\"authors\":\"Y. Greshishchev, P. Schvan\",\"doi\":\"10.1109/BIPOL.1999.803552\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An integrated 10 Gb/s clock and data recovery circuit implemented in IBM's SiGe technology is presented. It employs a linear type PLL based on a single-edge version of the Hogge type phase detector, an LC-VCO and a high-performance charge pump. Measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with -5 V power supply.\",\"PeriodicalId\":194523,\"journal\":{\"name\":\"Proceedings of the 1999 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.99CH37024)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-09-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1999 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.99CH37024)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1999.803552\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1999 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.99CH37024)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1999.803552","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
SiGe clock and data recovery IC with linear type PLL for 10 Gb/s SONET application
An integrated 10 Gb/s clock and data recovery circuit implemented in IBM's SiGe technology is presented. It employs a linear type PLL based on a single-edge version of the Hogge type phase detector, an LC-VCO and a high-performance charge pump. Measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with -5 V power supply.