J. Urresti, S. Hidalgo, D. Flores, J. Roig, J. Rebollo, J. Millán
{"title":"低压电视装置:设计与制造","authors":"J. Urresti, S. Hidalgo, D. Flores, J. Roig, J. Rebollo, J. Millán","doi":"10.1109/SMICND.2002.1105844","DOIUrl":null,"url":null,"abstract":"This paper addresses the optimisation of advanced transient voltage suppressor (TVS) devices for integrated circuit (IC) protection against electrostatic discharge (ESD) by means of technological and electrical simulations. An N/sup +/PP/sup +/N/sup +/ bipolar technology for low voltage (less than 3.3 V) TVs has been designed by optimising the trade-off between voltage capability and leakage current.","PeriodicalId":178478,"journal":{"name":"Proceedings. International Semiconductor Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Low voltage TVS devices: design and fabrication\",\"authors\":\"J. Urresti, S. Hidalgo, D. Flores, J. Roig, J. Rebollo, J. Millán\",\"doi\":\"10.1109/SMICND.2002.1105844\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper addresses the optimisation of advanced transient voltage suppressor (TVS) devices for integrated circuit (IC) protection against electrostatic discharge (ESD) by means of technological and electrical simulations. An N/sup +/PP/sup +/N/sup +/ bipolar technology for low voltage (less than 3.3 V) TVs has been designed by optimising the trade-off between voltage capability and leakage current.\",\"PeriodicalId\":178478,\"journal\":{\"name\":\"Proceedings. International Semiconductor Conference\",\"volume\":\"79 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. International Semiconductor Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMICND.2002.1105844\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. International Semiconductor Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.2002.1105844","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper addresses the optimisation of advanced transient voltage suppressor (TVS) devices for integrated circuit (IC) protection against electrostatic discharge (ESD) by means of technological and electrical simulations. An N/sup +/PP/sup +/N/sup +/ bipolar technology for low voltage (less than 3.3 V) TVs has been designed by optimising the trade-off between voltage capability and leakage current.
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