一种旨在提高TSC器件质量的综合方法

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI:10.1109/DFTVS.1999.802891

C. Bolchini, L. Pomante, D. Sciuto, F. Salice

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引用次数: 2

摘要

本文提出了一种提高组合TSC器件并发误差特性的综合方法。该方法基于对设备进行结构修改(可观测性修改)的迭代应用和对这种修改的影响的评估。采用全自检组合装置的成本函数进行质量评价，该函数除了考虑面积开销标准外，还考虑了不同方面，以比较不同的实现策略。该方法已在一组MCNC91基准测试中得到验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A synthesis methodology aimed at improving the quality of TSC devices

This paper proposes a synthesis methodology aimed at improving the concurrent error property of combinational TSC devices. The methodology is based on an iterative application of a structural modification of the device (observability modification) and an evaluation of the impact of such a modification. The quality evaluation is performed by means of a cost function for totally self-checking combinational devices which takes into account different aspects besides the area overhead criterion for comparing different realization strategies. The methodology has been validated on a set of MCNC91 benchmarks.

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来源期刊

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

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