一个易于扩展的基于FFT的四通道,四波束接收器,具有65nm的渐进部分空间滤波

Qingrui Meng, R. Harjani
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引用次数: 6

摘要

本文提出了一种基于FFT核的新型四通道四波束接收机核,该核易于扩展到更大的波束数。这种架构特别适用于使用多波束来提高吞吐量的MIMO系统。与FFT一样,所提出的体系结构可以重用多波束系统的计算。特别是,提出的架构重新分配计算,以最大限度地重用已经存在于接收链中的结构。在许多时尚中,架构与巴特勒矩阵非常相似,但与巴特勒矩阵不同的是,它在射频处不使用大型无源元件。此外,我们利用通常发生的正交下转换过程来实现抽头权重。与传统的MIMO体系结构相比,该体系结构的分布式计算在最后阶段之前提供了部分空间滤波,提高了LNA和ADC之间块的抗干扰性。此外,由于在ADC之前进行了空间滤波,单个干扰仅阻塞单个波束,从而允许在较低的综合吞吐量下继续操作。采用65nm CMOS的四波束接收器核心原型实现了基于FFT的基本架构,但不包括LNA或广泛的中频级。该四通道设计功耗为56mW,不包括焊盘和测试电路,其有效面积为0.65mm2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An easily extendable FFT based four-channel, four-beam receiver with progressive partial spatial filtering in 65nm
This paper presents a novel four-channel, four-beam receiver core based on a FFT core that is easily extended to a larger number of beams. This architecture is particulary well suited for MIMO systems where multiple beams are used for increased throughput. Like the FFT, the proposed architecture reuses computations for multi-beam systems. In particular, the proposed architecture redistributes the computations so as to maximize the reuse of the structure that already exist in a receiver chain. In many fashions the architecture is quite similar to a Butler matrix but unlike the Butler matrix it does not use large passive components at RF. Further, we exploit the normally occurring quadrature down-conversion process to implement the tap weights. In comparison to traditional MIMO architectures, that effectively duplicate each path, the distributed computations of this architecture provide partial spatial filtering before the final stage, improving interference rejection for the blocks between the LNA and the ADC. Additionally, because of the spatial filtering prior to the ADC, a single interferer only jams a single beam allowing for continued operation though at a lower combined throughput. The four-beam receiver core prototype in 65nm CMOS implements the basic FFT based architecture but does not include an LNA or extensive IF stages. This four-channel design consumes 56mW power and occupies an active area of 0.65mm2 excluding pads and test circuits.
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