一种CCD矩阵矩阵乘积并行处理器

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156578

A. Chiang, R. Mountain, D. Silversmith, B. Felton

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引用次数: 9

摘要

将报道一种工作频率高达10MHz的CCD矩阵器件的设计，该器件可执行雷达多普勒滤波所需的串行-输入并行-输出和傅立叶变换功能。该芯片包含32个乘法器和1024个累加器。

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A CCD matrix matrix product parallel processor

The design of a CCD matrix-matrix device operating up to 10MHz clock rates, performing the serial-in parallel-out and Fourier transform functions required in radar doppler filtering, will be reported. The chip contains 32 multipliers and 1024 accumulators.

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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