点阵解码算法的软硬件协同设计体系结构

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI:10.1109/FCCM.2006.47

C. Liang, Jing Ma, Xinming Huang

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引用次数: 0

摘要

针对MIMO系统中两种典型的点阵译码算法，提出了一种基于单FPGA的软硬件协同设计架构。分析了预处理部分在嵌入式MicroBlaze软处理器上实现，解码器部分在定制硬件上实现的两级并行性。AV解码器和VB解码器的系统原型表明，它们在XUP Virtex-II pro开发板上分别支持高达34.2 Mbps和3.15 Mbps的数据速率，比在DSP上实现分别快19倍和16倍

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Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms

This paper presents hardware/software co-design architecture targeted on a single FPGA for two typical lattice decoding algorithms in MIMO system. Two levels of parallelisms are analyzed for an efficient implementation with the preprocessing part on embedded MicroBlaze soft processor and the decoder part on customized hardware. The system prototypes of the AV and VB decoders show that they support up to 34.2 Mbps and 3.15 Mbps data rate respectively on XUP Virtex-II pro developing board, which are 19 and 16 times faster than their respective implementations on a DSP

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2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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