{"title":"GNSS软件接收机前端模块","authors":"J. Spacek, P. Puričer","doi":"10.1109/ELMAR.2006.329551","DOIUrl":null,"url":null,"abstract":"The topic of the paper is focused on the design and implementation of the radio front-end part for experimental GNSS software receiver developed at the Department of Radio Engineering of the Czech Technical University in Prague. The receiver is designed for the processing of signals of present and future global navigation satellite systems, including GPS, GLONASS and Galileo. For the biggest possible versatility, the modular architecture and software defined radio (SDR) concept were chosen. The front-end unit consists of three independent channels with the bandwidth of 24 MHz each that use a single conversion super-heterodyne concept with intermediate frequency 140 MHz. The front-end provides down converted analogue signal to DSP unit represented by FPGA device with two embedded PowerPC cores. The paper also provides comparison of the front-end of experimental receiver with lot manufacture case","PeriodicalId":430777,"journal":{"name":"Proceedings ELMAR 2006","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Front-end Module for GNSS Software Receiver\",\"authors\":\"J. Spacek, P. Puričer\",\"doi\":\"10.1109/ELMAR.2006.329551\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The topic of the paper is focused on the design and implementation of the radio front-end part for experimental GNSS software receiver developed at the Department of Radio Engineering of the Czech Technical University in Prague. The receiver is designed for the processing of signals of present and future global navigation satellite systems, including GPS, GLONASS and Galileo. For the biggest possible versatility, the modular architecture and software defined radio (SDR) concept were chosen. The front-end unit consists of three independent channels with the bandwidth of 24 MHz each that use a single conversion super-heterodyne concept with intermediate frequency 140 MHz. The front-end provides down converted analogue signal to DSP unit represented by FPGA device with two embedded PowerPC cores. The paper also provides comparison of the front-end of experimental receiver with lot manufacture case\",\"PeriodicalId\":430777,\"journal\":{\"name\":\"Proceedings ELMAR 2006\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings ELMAR 2006\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELMAR.2006.329551\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings ELMAR 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELMAR.2006.329551","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The topic of the paper is focused on the design and implementation of the radio front-end part for experimental GNSS software receiver developed at the Department of Radio Engineering of the Czech Technical University in Prague. The receiver is designed for the processing of signals of present and future global navigation satellite systems, including GPS, GLONASS and Galileo. For the biggest possible versatility, the modular architecture and software defined radio (SDR) concept were chosen. The front-end unit consists of three independent channels with the bandwidth of 24 MHz each that use a single conversion super-heterodyne concept with intermediate frequency 140 MHz. The front-end provides down converted analogue signal to DSP unit represented by FPGA device with two embedded PowerPC cores. The paper also provides comparison of the front-end of experimental receiver with lot manufacture case
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