FPGA互连中降低功耗的电荷回收

Safeen Huda, J. Anderson, H. Tamura
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引用次数: 5

摘要

我们提出电荷回收(CR)来降低fpga的功耗。我们利用了许多路由导体在任何应用的FPGA实现中都未使用的特性。通过未使用导体的电荷回收减少了从电源中吸取的电荷量,降低了能源消耗。我们提出了一种以正常和CR两种模式运行的路由开关,并描述了在流的路由和路由后阶段支持CR所需的CAD工具更改。结果表明,根据不同的性能限制,采用所提出的技术可将FPGA互连中的动态功率降低15-18.4%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Charge recycling for power reduction in FPGA interconnect
We propose charge recycling (CR) to reduce power consumption in FPGAs. We take advantage of the property that many routing conductors are left unused in any FPGA implementation of an application. Charge recycling via the unused conductors reduces the amount of charge drawn from the supply, lowering energy consumption. We present a routing switch that operates in two modes: normal and CR, and describe the CAD tool changes needed to support CR at the routing and post-routing stages of the flow. Results show that dynamic power in the FPGA interconnect can be reduced by up to ~15-18.4% by the proposed techniques, depending on the performance constraints.
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