具有多晶硅发射极结构的40 V BiCMOS技术

Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI:10.1109/ISPSD.1990.991065

S. Yamada, T. Yamauchi, M. Tokuriki, X. Inayoshi

{"title":"具有多晶硅发射极结构的40 V BiCMOS技术","authors":"S. Yamada, T. Yamauchi, M. Tokuriki, X. Inayoshi","doi":"10.1109/ISPSD.1990.991065","DOIUrl":null,"url":null,"abstract":"This paper describes a high voltage BiCMOS fabrication technique consisting of a selfaligned emitter process that uses reflowing PSG, photoetchs emitter contact windows and diffuses phosphorus in the windows through polysilicon. We also used a more lightly doped drain for NMOS transistors. As a result, we could fabricate bipolar transistors of over 40 V BV CEO and 1.56 GHz cutoff frequency ( fr ) and CMOS transistors of over 20 V BVDs.","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"40 V BiCMOS technology with polysilicon emitter structure\",\"authors\":\"S. Yamada, T. Yamauchi, M. Tokuriki, X. Inayoshi\",\"doi\":\"10.1109/ISPSD.1990.991065\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a high voltage BiCMOS fabrication technique consisting of a selfaligned emitter process that uses reflowing PSG, photoetchs emitter contact windows and diffuses phosphorus in the windows through polysilicon. We also used a more lightly doped drain for NMOS transistors. As a result, we could fabricate bipolar transistors of over 40 V BV CEO and 1.56 GHz cutoff frequency ( fr ) and CMOS transistors of over 20 V BVDs.\",\"PeriodicalId\":162198,\"journal\":{\"name\":\"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-04-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1990.991065\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1990.991065","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文介绍了一种高压BiCMOS制造技术，该技术由自调谐发射极工艺组成，该工艺使用回流PSG，光蚀刻发射极接触窗口并通过多晶硅扩散磷。我们还为NMOS晶体管使用了更轻掺杂的漏极。因此，我们可以制造出超过40 V BV的双极晶体管和1.56 GHz的截止频率(fr)和超过20 V bvd的CMOS晶体管。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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40 V BiCMOS technology with polysilicon emitter structure

This paper describes a high voltage BiCMOS fabrication technique consisting of a selfaligned emitter process that uses reflowing PSG, photoetchs emitter contact windows and diffuses phosphorus in the windows through polysilicon. We also used a more lightly doped drain for NMOS transistors. As a result, we could fabricate bipolar transistors of over 40 V BV CEO and 1.56 GHz cutoff frequency ( fr ) and CMOS transistors of over 20 V BVDs.

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Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.

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