SiC mosfet偏置应力不稳定性的建模与表征

2006 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2006-10-01 DOI:10.1109/IRWS.2006.305235

A. Lelis, S. Potbhare, D. Habersat, G. Pennington, N. Goldsman

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引用次数: 2

摘要

在SiC mosfet中观察到由偏置应力引起的阈值电压不稳定。在高栅极偏置下的应力会引起SiC mosfet阈值电压高达几百毫伏的偏移，从而显著影响电路性能。我们试图通过实验和数值模拟分析来表征这种阈值电压不稳定性。我们看到明显的不稳定性，应力时间小于10秒，应力电压低至4V。实验与仿真对比表明，这种阈值电压不稳定是由于过量的氧化物捕获电荷引起的，而且这种不稳定是可逆的

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Modeling and Characterization of Bias Stress-Induced Instability of SiC MOSFETs

Threshold voltage instability due to bias stressing has been observed in SiC MOSFETs. Stressing at high gate bias has caused shifts up to several hundred millivolts in the threshold voltage of SiC MOSFETs which can significantly affect circuit performance. We have tried to characterize this threshold voltage instability by experimental and numerical modeling analyses. We see appreciable instability for stress times as less as 10s and stress voltages as low as 4V. Comparison of experiment and simulation indicates that this threshold voltage instability is caused due to excess oxide trapped charge, and also that the instability is reversible

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2006 IEEE International Integrated Reliability Workshop Final Report

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