表面优化对200mm晶圆级封装研磨后成品率的影响

M. Inac, M. Wietstruck, A. Göritz, B. Çetindoğan, C. Baristiran-Kaynak, M. Lisker, A. Krüger, U. Saarow, P. Heinrich, T. Voß, Kasim Altin, M. Kaynak
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引用次数: 0

摘要

本文介绍了在200mm晶圆级封装应用中,后磨能提高成品率的方法。晶圆封装采用200mm晶圆级等离子体增强氧化-氧化直接结合和晶圆研磨工艺。由于用于封装的晶圆的表面状况是晶圆键合和研磨过程中最关键的一点,因此重点关注优化晶圆表面以提高良率。对封装用BiCMOS晶圆的表面条件进行优化后,200 mm等离子体增强的晶圆间直接键合成品率从0%提高到99%,同时这些晶圆的研磨后成品率从0%提高到90%以上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The Effect of Surface Optimization on Post-grinding Yield of 200 mm Wafer Level Packaging Applications
In this paper, a yield increase on post-grinding of 200 mm wafer level packaging applications is presented. 200 mm wafer level plasma enhanced oxide-oxide direct bonding and wafer grinding are used in the packaging of the wafers. Since the surface conditions of the wafers that are used in the packaging is the most critical point of the wafer bonding and grinding processes, it is focussed to optimizing wafer surfaces to increase the yield. After the optimizations on the surface conditions of the BiCMOS wafer used in the packaging, the 200 mm plasma enhanced wafer to wafer direct bonding yield increases from 0% to 99% and at the same time the post-grinding yield of these wafers increases from 0% to over 90%.
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