低漏DRAM电池垂直沟道纳米级mosfet模拟

2006 IEEE Nanotechnology Materials and Devices Conference Pub Date : 2006-10-01 DOI:10.1109/NMDC.2006.4388879

Seung-Hyun Song, Jeong-Soo Lee, Y. Jeong

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引用次数: 0

摘要

提出了一种用于低漏动态随机存取存储器(DRAM)单元的垂直沟道纳米级MOSFET。由于垂直沟道结构的沟道长度比常规规划结构长，因此可以显著降低短沟道效应(SCE)。该结构具有源扩展以增强阈下摆动(SS)，以及颈部侧壁间隔器以减少栅诱发漏漏(GIDL)。

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Simulation of vertical channel nanoscale MOSFETs for low leakage DRAM cell

A vertical channel nanoscale MOSFET for low leakage dynamic random access memory (DRAM) cell is proposed. Due to longer channel length than that of the conventional planner structure, the vertical channel structure can dramatically reduce short channel effect (SCE). This structure features a source extension to enhance subthreshold swing (SS), and a neck sidewall spacer to reduce gate induced drain leakage (GIDL).

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2006 IEEE Nanotechnology Materials and Devices Conference

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