高性能asic的I/O阻抗匹配算法

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI:10.1109/ASIC.1997.617019

P. Zuchowski, J. H. Panner, D. Stout, J. Adams, F. Chan, P. Dunn, A. D. Huber, J. J. Oler

{"title":"高性能asic的I/O阻抗匹配算法","authors":"P. Zuchowski, J. H. Panner, D. Stout, J. Adams, F. Chan, P. Dunn, A. D. Huber, J. J. Oler","doi":"10.1109/ASIC.1997.617019","DOIUrl":null,"url":null,"abstract":"This paper discusses a design style that utilizes an area array of flip-chip solder bump connections, I/O circuit designs that implement a programmable impedance matching algorithm, and a design system that must utilize these features during chip layout, chip checking, and release to manufacturing. Results from a recent test chip are also given.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"I/O impedance matching algorithm for high-performance ASICs\",\"authors\":\"P. Zuchowski, J. H. Panner, D. Stout, J. Adams, F. Chan, P. Dunn, A. D. Huber, J. J. Oler\",\"doi\":\"10.1109/ASIC.1997.617019\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses a design style that utilizes an area array of flip-chip solder bump connections, I/O circuit designs that implement a programmable impedance matching algorithm, and a design system that must utilize these features during chip layout, chip checking, and release to manufacturing. Results from a recent test chip are also given.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.617019\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.617019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

摘要

本文讨论了一种设计风格，该设计风格利用倒装芯片焊接凸点连接的面积阵列，实现可编程阻抗匹配算法的I/O电路设计，以及在芯片布局，芯片检查和释放到制造过程中必须利用这些功能的设计系统。最后给出了一种新型测试芯片的测试结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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I/O impedance matching algorithm for high-performance ASICs

This paper discusses a design style that utilizes an area array of flip-chip solder bump connections, I/O circuit designs that implement a programmable impedance matching algorithm, and a design system that must utilize these features during chip layout, chip checking, and release to manufacturing. Results from a recent test chip are also given.

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来源期刊

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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