{"title":"异步顺序电路的高性能计算合成","authors":"František Kudlačák, E. Gramatová","doi":"10.1109/BEC.2014.7320557","DOIUrl":null,"url":null,"abstract":"The paper deals with asynchronous sequential circuits synthesis based on finite state machine representation at the logical level. A new computer-aided design (CAD) system has been developed using the finite state machine description in VHDL and a new design algorithm for generating a synthesized circuit model in VHDL. The developed CAD system was implemented for the single-processor system and also the high-performance computing system. Effectiveness of the new CAD system was evaluated on the high-performance computing system using different numbers of computational nodes by various types of finite state machines.","PeriodicalId":348260,"journal":{"name":"2014 14th Biennial Baltic Electronic Conference (BEC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Asynchronous sequential circuits synthesis by high-performance computing\",\"authors\":\"František Kudlačák, E. Gramatová\",\"doi\":\"10.1109/BEC.2014.7320557\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper deals with asynchronous sequential circuits synthesis based on finite state machine representation at the logical level. A new computer-aided design (CAD) system has been developed using the finite state machine description in VHDL and a new design algorithm for generating a synthesized circuit model in VHDL. The developed CAD system was implemented for the single-processor system and also the high-performance computing system. Effectiveness of the new CAD system was evaluated on the high-performance computing system using different numbers of computational nodes by various types of finite state machines.\",\"PeriodicalId\":348260,\"journal\":{\"name\":\"2014 14th Biennial Baltic Electronic Conference (BEC)\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 14th Biennial Baltic Electronic Conference (BEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BEC.2014.7320557\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 14th Biennial Baltic Electronic Conference (BEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BEC.2014.7320557","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Asynchronous sequential circuits synthesis by high-performance computing
The paper deals with asynchronous sequential circuits synthesis based on finite state machine representation at the logical level. A new computer-aided design (CAD) system has been developed using the finite state machine description in VHDL and a new design algorithm for generating a synthesized circuit model in VHDL. The developed CAD system was implemented for the single-processor system and also the high-performance computing system. Effectiveness of the new CAD system was evaluated on the high-performance computing system using different numbers of computational nodes by various types of finite state machines.
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